#define store_x sw
#define load_x lw
#define portWORD_SIZE 4
#define portCONTEXT_SIZE ( 32 * portWORD_SIZE )
.section .init
.global _startup
_startup:
j start
trap_entry:
j trap
start:
lui sp,%hi(0x000EFFC)
addi sp,sp,%lo(0x000EFFC)


lui a1,%hi(0x000FFFC)
addi a1,a1,%lo(0x000FFFC)

csrrw x0,mstatus,a1
addi a0,x0,0
//切换到寄存器组1
/* lui a0,%hi(0xffffffff)
addi a0,a0,%lo(0xffffffff)
csrrw x0,mie,a0//开中断 */
addi a0 ,x0,0
csrrw x0,mie,a0
csrrw x0,mcause,a0
csrrw x1,0xfff,x2
addi a0,x0,0
.option push 
.option	norelax 
	la gp, __global_pointer$
.option	pop 
2:
 	/* Load data section from flash to RAM */
 	la a0, _data_lma
 	la a1, _data_vma
 	la a2, _edata
 	bgeu a1, a2, 2f
 1:
 	lw t0, (a0)
 	sw t0, (a1)
 	addi a0, a0, 4
 	addi a1, a1, 4
 	bltu a1, a2, 1b
 2:
 	/* clear bss section */
 	la a0, _sbss
 	la a1, _ebss
 	bgeu a0, a1, 2f
 1:
 	sw zero, (a0)
 	addi a0, a0, 4
 	bltu a0, a1, 1b
 2:
 
 la t0, main
 csrw mepc, t0
 mret
.extern printInt
.extern pxCurrentTCB
.extern mmp
trap:
    addi sp, sp, -portCONTEXT_SIZE
    store_x x1, 0 * portWORD_SIZE( sp )
    store_x x2, 1 * portWORD_SIZE( sp )
	store_x x3, 2 * portWORD_SIZE( sp )
	store_x x4, 3 * portWORD_SIZE( sp )
	store_x x5, 4 * portWORD_SIZE( sp )
	store_x x6, 5 * portWORD_SIZE( sp )
	store_x x7, 6 * portWORD_SIZE( sp )
	store_x x8, 7 * portWORD_SIZE( sp )
	store_x x9, 8 * portWORD_SIZE( sp )
	store_x x10, 9 * portWORD_SIZE( sp )
	store_x x11, 10 * portWORD_SIZE( sp )
	store_x x12, 11 * portWORD_SIZE( sp )
	store_x x13, 12 * portWORD_SIZE( sp )
	store_x x14, 13 * portWORD_SIZE( sp )
	store_x x15, 14 * portWORD_SIZE( sp )
	store_x x16, 15 * portWORD_SIZE( sp )
	store_x x17, 16 * portWORD_SIZE( sp )
	store_x x18, 17 * portWORD_SIZE( sp )
	store_x x19, 18 * portWORD_SIZE( sp )
	store_x x20, 19 * portWORD_SIZE( sp )
	store_x x21, 20 * portWORD_SIZE( sp )
	store_x x22, 21 * portWORD_SIZE( sp )
	store_x x23, 22 * portWORD_SIZE( sp )
	store_x x24, 23 * portWORD_SIZE( sp )
	store_x x25, 24 * portWORD_SIZE( sp )
	store_x x26, 25 * portWORD_SIZE( sp )
	store_x x27, 26 * portWORD_SIZE( sp )
	store_x x28, 27 * portWORD_SIZE( sp )
	store_x x29, 28 * portWORD_SIZE( sp )
    store_x x30, 29 * portWORD_SIZE( sp )
    store_x x31, 30 * portWORD_SIZE( sp )
	csrrw a1,mepc,x0
	store_x a1, 31 * portWORD_SIZE( sp )
	la t0 , pxCurrentTCB
	lw t0, 0(t0)
	store_x  sp, 0( t0 )//stack write to tcb
    csrrw sp,mstatus,sp
    csrrw a0,mcause,x0
    
    call irq
    
	lui a1,%hi(0x80000000)
	csrrw a0,mcause,x0
	and a0,a1,a0
	
	

	addi sp,sp,-8
	sw x1,4(sp)
	call process_task

	lw x1,4(sp)
	addi sp,sp,8

	addi a0,x0,0
    csrrw x0,mcause,a0//清中断


    csrrw sp,mstatus,sp
	la t0 , pxCurrentTCB//恢复sp
	lw t0,0(t0)
	lw t0,0(t0)

	addi sp,t0,0//恢复sp

	load_x  a1, 31 * portWORD_SIZE( t0 )//获取mepc
	csrrw x0,mepc,a1//恢复mepc

	
	
    load_x  x1, 0 * portWORD_SIZE( sp )
    load_x  x2, 1 * portWORD_SIZE( sp )
	load_x  x3, 2 * portWORD_SIZE( sp )		/* t0 */
	load_x  x4, 3 * portWORD_SIZE( sp )		/* t1 */
	load_x  x5, 4 * portWORD_SIZE( sp )		/* t2 */
	load_x  x6, 5 * portWORD_SIZE( sp )		/* s0/fp */
	load_x  x7, 6 * portWORD_SIZE( sp )		/* s1 */
	load_x  x8, 7 * portWORD_SIZE( sp )	/* a0 */
	load_x  x9, 8 * portWORD_SIZE( sp )	/* a1 */
	load_x  x10, 9 * portWORD_SIZE( sp )	/* a2 */
	load_x  x11, 10 * portWORD_SIZE( sp )	/* a3 */
	load_x  x12, 11 * portWORD_SIZE( sp )	/* a4 */
	load_x  x13, 12 * portWORD_SIZE( sp )	/* a5 */
	load_x  x14, 13 * portWORD_SIZE( sp )	/* a6 */
	load_x  x15, 14 * portWORD_SIZE( sp )	/* a7 */
	load_x  x16, 15 * portWORD_SIZE( sp )	/* s2 */
	load_x  x17, 16 * portWORD_SIZE( sp )	/* s3 */
	load_x  x18, 17 * portWORD_SIZE( sp )	/* s4 */
	load_x  x19, 18 * portWORD_SIZE( sp )	/* s5 */
	load_x  x20, 19 * portWORD_SIZE( sp )	/* s6 */
	load_x  x21, 20 * portWORD_SIZE( sp )	/* s7 */
	load_x  x22, 21 * portWORD_SIZE( sp )	/* s8 */
	load_x  x23, 22 * portWORD_SIZE( sp )	/* s9 */
	load_x  x24, 23 * portWORD_SIZE( sp )	/* s10 */
	load_x  x25, 24 * portWORD_SIZE( sp )	/* s11 */
	load_x  x26, 25 * portWORD_SIZE( sp )	/* t3 */
	load_x  x27, 26 * portWORD_SIZE( sp )	/* t4 */
	load_x  x28, 27 * portWORD_SIZE( sp )	/* t5 */
	load_x  x29, 28 * portWORD_SIZE( sp )	/* t6 */
    load_x  x30, 29 * portWORD_SIZE( sp )	/* t6 */
    load_x  x31, 30 * portWORD_SIZE( sp )	/* t6 */
    addi sp, sp, portCONTEXT_SIZE
    mret
process_task:
	
	beq a0,x0,process_task_end
	addi sp,sp,-8
	sw x1,4(sp)

	.insn u 0x77,x2,0x20//,a0
	jal vTaskSwitchContext
	lw x1,4(sp)

	addi sp,sp,8

	
process_task_end:
	ret
.global set_reg
set_reg:
    .insn r 0x77,0,1,a0,a0,x0
    ret
.global get_reg
get_reg:
    .insn r 0x77,0,0,a0,a1,x0
    ret
.global set_irq
set_irq:
	csrrw x0,mie,a0
	ret
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

